The present invention relates to a method for assisting in the design of a logic circuit in the placement of cells on an IC substrate and in the optimization of wiring, a device for assisting in the design of a logic circuit using this method, and a computer program executable by this device.
When designing a complicated semiconductor integrated circuit, the logic circuit may have several levels. In order to simplify the logic design in the upper levels, the logic circuits in the lower levels can be black-boxed. The design of the levels is not expanded when the logic is designed. The levels are expanded when the wiring is verified, and are usually verified as logic circuits with a single-level structure. A typical design method of the prior art is disclosed in Japanese Patent No. 4,679,029. FIG. 11 is a diagram illustrating this logic circuit design method of the prior art.
As shown in FIG. 11(a), a logic circuit on which logic operation elements (cells) have been placed and wiring optimized has been realized on an IC substrate. In order to realize this, placement areas (blocks) are established for the placement of cells which are divided on a grid as shown in FIG. 11(b), and one cell is placed in each block corresponding to a portion of the grid. There are no particular restrictions on the algorithm used to place cells. The cells can be placed, for example, using the “Min-Cut” method.
Then, as shown in FIG. 11(c), the positions of the cells are adjusted to wire the placed cells and minimize the sum total of wire lengths or the overall wiring length. When designing a complicated semiconductor integrated circuit, the logic design is simplified by creating multiple levels of logic circuits and black-boxing the logic circuits on the lower levels. FIG. 12 is a diagram illustrating a level of a hierarchical logic circuit.
In the logic circuit MacA shown in FIG. 12(a), the designing method in FIG. 11 is used to establish placement areas (blocks) for the placement of cells as shown in FIG. 12 (b), and a cell is placed in each block. Then, the positions of the cells are adjusted to wire the placed cells and minimize the overall wiring length.
Next, logic circuit MacA is black-boxed and treated as a single cell in the design of the logic circuits in higher levels. FIG. 13 is a diagram illustrating a logic circuit design method for an upper level in which logic circuit MacA has been black-boxed.
As shown in FIG. 13(a), logic circuit MacA is black-boxed, and treated as a single cell. A single cell is then placed in each block as shown in FIG. 13(b). In this way, the types and number of logic operation elements (cells) handled at this point in the logic design can be reduced, the resources required to place and wire cells are reduced, and a logic circuit can be designed more efficiently.